The present invention relates to a deskew circuit and a deskew method that corrects skews between clock and data, as well as among data on a data bus, in data transfers to transfer large volume data between packages at high-speed and to transfer clock and data in parallel.
A conventional technology that transmits data at high-speed while taking data skew into consideration has been indicated. In such a technology, a delay amount for every bit in data on the receiving side is adjusted using a phase adjustment pattern. However, phases are matched to an external clock supplied to both the transmitting and receiving sides, and the technology therefore is not a method to transfer clock and data in parallel.
The conventional technology involves a method of adjusting only the clock in devices such as disk array control devices in which there is a large skew in a backplane due to the large number of packages and in which a high-speed transfer must be implemented in a data transfer method that transfers clock and data (bus data) in parallel in order to reduce power consumption. Although this method is effective when the transfer speed is slow and data pulse width is wide, it is difficult to correct the clock to a position that allows all data to be read correctly when the transfer speed is fast and the data pulse width is narrow. This becomes even more difficult when taking into consideration the junction temperature fluctuations of an LSI that has a built-in circuit that makes such an adjustment, power source voltage fluctuations, flip flop set-up time and hold time. Further, the skew is small and the clock can be corrected when the transmission distance is short (e.g., approximately 10 cm–20 cm), such as when sending and receiving within the same substrate (package). However, the skew is larger and correcting the dock become very difficult when the transmission distance is long (e.g., approximately dozens to 100 cm), such as in a backplane. Skew adjustment becomes difficult when the transmission distance is long as in a backplane, and this also sets a limit to the transfer speed and makes high-speed transfer impossible.